Commit 0cfc3341 authored by Bjarne Wintermann's avatar Bjarne Wintermann
Browse files

Can now also accept AXILite and AXI Bus Interfaces

parent c3ac29be
......@@ -12,6 +12,9 @@ from termcolor import colored
def say(s, error=False):
print(colored(s, ('green' if not error else "red")))
from litex.soc.interconnect.axi import *
class SignalMonitor(Module):
"""
This unit can monitor given signals and, when a trigger occurs, write the current values of those signals into a queue.
......@@ -128,6 +131,20 @@ class BusMasterMonitor(Module):
multipleMasters = type(masterInterface) == list
mInterfaces = [("0", masterInterface)] if not multipleMasters else [(str(i), masterInterface[i]) for i in range(len(masterInterface))]
# Convert to wishbone if the interfaces are AXI or AXILite
tmp = []
for idx, mint in mInterfaces:
if type(mint) == wishbone.Interface:
i = mint
elif type(mint) == AXILiteInterface:
i = axil2wb(mint)
elif type(mint) == AXIInterface:
i = axi2wb(mint)
tmp.append((idx, i))
mInterfaces = tmp
# Add signals for all masters. These are recorded
data = {}
for index, mint in mInterfaces:
......@@ -278,4 +295,14 @@ class BusMasterMonitor(Module):
def getCompleteLayoutWidth(self):
"""Width of the recording layout / the output queue"""
return sum(self.getRecordedSignalLengths())
\ No newline at end of file
return sum(self.getRecordedSignalLengths())
def axil2wb(self, interface: AXILiteInterface) -> wishbone.Interface:
wb = wishbone.Interface(data_width=self.dmaBus.data_width, adr_width=dmaBus.address_width)
self.submodules += AXILite2Wishbone(interface, wb)
return wb
def axi2wb(self, interface: AXIInterface) -> wishbone.Interface:
wb = wishbone.Interface(data_width=self.dmaBus.data_width, adr_width=dmaBus.address_width)
self.submodules += AXI2Wishbone(interface, wb)
return wb
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