Commit f76a827e authored by Bjarne Wintermann's avatar Bjarne Wintermann
Browse files


parent 0a44e700
......@@ -48,3 +48,6 @@ litebusmonitor/firmware/
The LiteBusMonitor component is a LiteX component for the purpose of monitoring and recording bus transactions of a SoC. (WIP: To be used in combination with the security/rule-enforcer type component to act on suspicious bus transactions).
componentNode/.style={rectangle, draw=green!60, fill=green!5, very thick, minimum size=7mm},
litexNode/.style={rectangle, draw=blue!60, fill=blue!5, very thick, minimum size=7mm},
busNode/.style={rectangle, draw=yellow!60, fill=yellow!5, very thick, minimum size=7mm, minimum width=10cm},
cpuNode/.style={rectangle, draw=red!60, fill=red!5, very thick, minimum size=7mm},
memoryNode/.style={rectangle, draw=cyan!60, fill=cyan!15, very thick, minimum size=7mm, minimum height=3cm, minimum width = 3cm}
% \node[depth=3cm](soc){SoC}
\node[componentNode] (mc) at (0,0){Monitoring Component}; % at (
\node[componentNode](bm) at (0,-2) {Bus Monitor};
\node[componentNode](sm) at (0,-4) {Signal Monitor};
%\node[litexNode](dma) at (0, 2) {DMA};
\node[busNode] (bn2) at (0,3) {Bus Master 2};
\node[busNode] (bn1) at (0,4) {Bus Master 1};
\node[busNode] (mcbm) at (0,2) {Monitor Component Bus Master};
\node[cpuNode] (cpu) at (-4, 0) {CPU};
\node[memoryNode] (mem) at (-8,|- bn2) {Memory};
\draw[<->] (mc.south) -- (bm.north);
\draw[<->] (bm.south) -- (sm.north);
%\draw[->] (mc.north) -- (dma.south);
\draw[<->] (cpu.north west) -- (cpu.north west |- bn1.south);
\draw[<->] (cpu.north east) -- (cpu.north east |- bn2.south);
%\draw[<->] (dma.north) -- (mcbm.south);
\draw[<->] (cpu.east) -- (mc.west) node[midway, above] {CSRs};
\draw[->] (bn1.east) -- (5.5, |-;
\draw[->] (bn2.east) -- (5.5, |-;
\draw[->] (5.5, |- -- (5.5, |- -- (mc.east);
\draw[<->] (bn1.west) -- (mem.east |- bn1.west);
\draw[<->] (bn2.west) -- (mem.east |- bn2.west);
\draw[<->] (mcbm.west) -- (mem.east |- mcbm.west);
\node[fit=(mc)(bm)(sm)(bn2)(bn1)(cpu)(mem)(mcbm), draw, very thick, draw=gray, inner sep=1cm] (soc) {};
\node[below right] at (soc.north west) {SoC};
\section*{Signal Monitor}
The most basic component of the package is the \textit{SignalMonitor} module. It takes a list of trigger signals or migen statements, a triggerMode that determines the type of trigger (rising, falling, changing, high, etc.) and a dictionary of signals to monitor with their names as keys. Internally the entries that get recorded are saved in a queue, accessible via the SignalMonitor's source attribute.
\begin{tikzpicture}[componentNode/.style={rectangle, draw=green!60, fill=green!5, very thick, minimum size=2cm}]
\node[componentNode] (q) {FIFO};
\node[fit=(q), inner sep=3cm, draw, very thick, draw=gray] (signalmonitor) {};
\node[below right] at (signalmonitor.north west) {SignalMonitor};
\node[left= of signalmonitor, minimum height=2cm] (recordSignals) {};
\node[above= of recordSignals] (triggerSignals) {};
\draw[->, very thick] (recordSignals.east) -- (signalmonitor.west);
\draw[->, thick] (triggerSignals.east) -- (triggerSignals.east -| signalmonitor.west);
\draw[->, very thick] (signalmonitor.west) -- (q.west) node[midway, above] {Record Signals};
\draw[-, thick] (triggerSignals.east -| signalmonitor.west) -- (triggerSignals.east -| q.north) node[midway, above] {Trigger Signals};
\draw[->, thick] (triggerSignals.east -| q.north) -- (q.north);
\draw[->, very thick] (q.east) -- (signalmonitor.east);
\node[right= of signalmonitor] (fifoout) {};
\draw[->, very thick] (signalmonitor.east) -- (fifoout.west);
\ No newline at end of file
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