First finished Version using LiteX Still needs to change the BIOS to work, but now supports recording and receiving/decoding on different devices.
Currently configured to read out boot/bios. Monitoring Component works, C firmware works, decode3.py works and decodes the data. Reading rate around 300 KB/s and decoding around 70-100 KB/s. Issue to fix: Some blocks are missing when decoding, presumably because the end-of-block sign was not read correctly, but if this is the case it only affects around ~2% of blocks usually.
Faster recording time since raw bytes get transferred. This commit uses a pre-loaded ROM: The firmware gets packet into the bitstream (rebuild everytime you change it) the baudrate everywhere is set to 5 000 000 and an add_rom() call reserves space for the firmware at 0x30000000. The linker script got changed for that as well
Monitor working with the VexRiscV softcore (IRQs not yet implemented for other cores). Interrupts stop execution to write the data out on UART. Internally saves memory as an array of 32-bit words, layouting of which is given by the generated predefined.h/.c files and decoding of which is provided by decoder.c. The decoder >script< in litebusmonitor/tools/ can be run to capture the serial output of the board and store it in a csv file. Documentation for the different parameters is given as well. There are some larger readouts available, the largest in zipped file format. It holds records of the boot process, starting from the beginning of the BIOS's __main__ method, missing only around 21k bus accesses in the beginning and none afterwards.